With the trend of reduction in current consumption, a logic-type input signal supplied from an IC tends to be lowered in voltage and thus generally converged to 3.3V or 5V. However, reduction in driving voltage of the drive circuit on the panel or in application voltage to liquid crystal to be less than the existing 8V or 12V can be achieved only by improvement in process or material, and therefore not easy. This means it is indispensable to carry out level shift of the input signal from IC. Accordingly, operation of the logic circuit on the panel or the liquid crystal driving circuit section requires a power-source-voltage level conversion circuit; otherwise, the driving have to be performed with a signal modified in voltage in the driver IC. In the former case, the circuit structure preferentially needs some kind of low current consumption strategy to reduce feed-through current as much as possible. This requires a larger number of Trs, making the internal delay more significant. The following describes such a liquid crystal display device having a level shifter on the panel.
First, a liquid crystal display device having a display panel 501 shown in FIG. 31 is described. The display panel 501 includes gate bus lines GL . . . , source bus lines SL . . . corresponding to RGB, and a pixel at each intersection of those bus lines GL and SL. When display is performed in the display panel 501, a source driver 503 writes a video signal to a pixel of the gate bus line GL selected by a gate driver 502, via the source bus lines SL. Note that, each pixel includes a liquid crystal capacitor, an auxiliary capacitor, and a TFT for fetching a video signal from the source bus line SL, one end of the respective auxiliary capacitors being connected one another by an auxiliary capacitor line called a Cs-Line.
The display panel 501 includes a sampling circuit block 501a, that is made up of analog switches ASW, provided for the respective source bus line SL, for sampling video signals, and control signal processing circuits (sampling buffer etc.) for the switches. The source driver 503 outputs signals (sampling pulse) indicating ON/OFF state of the sampling switch ASW for each group consisting of RGB source bus lines SL. Each of RGB lines has an individual video signal transmission line, allowing simultaneous but individual sampling for RGB from the switches ASW; however, in this example, a signal is fetched from a common video signal transmission line to the all sampling switches ASW of RGB. Note that, the sampling switches ASW may be controlled by a common sampling pulse, or by different pulses for RGB.
In a horizontal period, for example, the source bus line SL of R sequentially captures externally supplied video signals DATA by turning on the analog switches ASW (R1), . . . , ASW (Ri−1), ASW (Ri), ASW (Ri+1), . . . , that are connected to the source bus lines SL of R, in this order, by the sampling pulses. In this manner, sequential video signal writing is carried out.
FIG. 22 shows an arrangement example of the source driver 503 outputting sampling signals to the analog switches ASW (1), . . . , (i−1), (i), (i+1), . . . in this order.
As shown in the figure, a conventional source driver of a full-monolithic panel includes a shift register, and a level shifter that performs power-source-voltage conversion to drive the shift register. With this arrangement, the source driver produces sampling pulses for the analog switches ASW for each source bus line SL. The shift register is made of a plurality of set-reset flip-flops in cascade connection, denoted by SR-FF in the figure, each of the adjacent pair has a level shifter (denoted by LS) therebetween. The example shown in the figure is one corresponding to a group consisting of i, i+1, and i+2, but each of any other groups has one set-reset flip-flop and one corresponding level shifter. Hereinafter, the i-th set-reset flip-flop is expressed as a flip-flop FF (i), and the i-th level shifter is expressed as a LS (i).
The level shifter LS carries out power-source-voltage exchange when an active signal is supplied to an enable terminal ENA, and clock signals SCK and SCKB are supplied to the input terminals CK and CKB of the LS. The clock signals SCK and SCKB are opposite in phase. An output terminal OUTB is connected to an inversion set input terminal SB in the same group. The enable terminal ENA is connected to the output terminal Q in the immediately preceding stage. The input terminals CK and CKB are respectively supplied with one of the clock signals SCK and SCKB; for example, CK is supplied with SCK and CKB is supplied with SCKB, or other way round, depending on whether it is an odd numbered group or even numbered group. In this example, the clock signals CK and SCK are supplied to the input terminals CKB and SCKB of the level shifter LS(i), respectively. A reset terminal R of one flip-flop FF is connected to the output terminal Q of the flip-flop FF in the next stage.
In such a structure of the panel, the following explains a relation between the clock signal SCK and the output signal of the flip-flop FF with reference to FIG. 23. Hereinafter, output from the output terminal Q of the i-th flip flop FF is referred to as an output signal Q (i).
When the clock signal SCK rises from low level to high level and the clock signal SCKB falls from high level to low level while a high level, that is an active signal, is supplied to the enable terminal ENA of LS (i), the clock signal SCK, that has been converted in voltage and inverted in phase, is outputted from the output terminal OUTB. The output signal is supplied to the inversion set input terminal SB of the flip-flop FF (i), and an inversion signal, i.e., a high level is outputted as an output signal Q from the output terminal Q. Here, the level shifter LS (i+1) outputs a high level from the output terminal OUTB, and therefore the output signal Q (i+1) of the flip-flop FF (i+1) becomes low level. As a result, a low level is supplied to the reset terminal R of the flip-flop FF(i).
Next, when the clock signal SCK falls from high level to low level, and the clock signal SCKB rises from low level to high level, a low level is outputted from the output terminal OUTB of the level shifter LS (i+1), and therefore the output signal Q (i+1) of the flip-flop FF (i+1) becomes high level. As a result, a high level is supplied to the reset terminal R of the flip-flop FF (i) and the output signal Q (i) falls from high level to low level. The output signal Q (i+1) is kept at high level until a high level output signal Q (i+2) is supplied from the output terminal Q of the flip-flop FF (i+2) to the reset terminal R of the flip-flop FF (i+1) in the same manner.
Further, when the clock signal SCK rises from low level to high level and the clock signal SCKB falls from high level to low level while the output signal Q (i+1) is at high level, a low level is outputted from the output terminal OUTB of the flip-flop FF (i+2), and therefore the output signal Q (i+2) of the flip-flop FF (i+2) becomes high level.
In this manner, as shown in FIG. 23, the output pulses, i.e., the high level output signals Q (i), Q (i+1), and Q (i+2) are sequentially outputted in chronological order. More specifically, in a horizontal period of one of the gate bus line GL, the output pulses, i.e., the high level output signals Q (i), Q (i+1), and Q (i+2) are sequentially outputted. Such a signal output is performed simultaneously but individually for RGB.
However, as can be seen in the figure, the rise of the output signal Q (i) is delayed by a time Ta (delay time) from the rise of the clock signal SCK. The delay time Ta is sum of the internal delay time of the level shifter LS and the internal delay time of the flip-flop FF. Further, the fall of the output signal Q (i) is delayed by a time Tb, that is the internal delay time of the flip-flop FF, from the rise of the output signal Q (i+1). Accordingly, the Q (i) is delayed by Ta+Tb from the fall of the clock signal SCK. As a result, the fall state of the output signal Q (i) and the rise state of the output signal Q (i+1) are partly overlapped, where these signals are both at high level. Like so, the adjacent output pulses are overlapped with each other due to the delay times.
As mentioned above, the output pulses are used for sampling of video signals DATA. Therefore, if there are any overlapped periods, supply of the video signal DATA to the next stage source bus line and the pixel is started during the writing period (charging period) of the video signal DATA to the corresponding source bus line and the pixel thereof. As a result, the data writing for the next stage source bus line and the pixel is carried out in the writing period of the prior stage, thus failing proper writing to the pixel, and may result in some kind of display defect, such as ghost.
One conventional method of solving such a defect in display can be found in a prior art Document 1 (Japanese laid-open patent application Tokukaihei 11-272226, published on Oct. 8, 1999), the structure thereof is shown in FIG. 22, wherein a delay circuit delay is added to the output section to cause some delay of the output pulses of the output signals Q (1), . . . , Q (i), Q (i+1), Q (i+2), . . . , so that the rise of each output pulse is delayed on purpose, thus preventing the overlap. As shown in FIG. 24, the delay circuit delay causes delay of the output pulse using a NAND circuit that is supplied with the output signal Q (i) and the output signal Q having been through a plurality of inverters. With the use of this NAND circuit, as denoted by the waveform of SMP in FIG. 25, the rise of the sampling pulse is delayed from the rise of the output pulse.
Next to the delay circuit delay, there is provided a level shifter for converting the power-source voltage level according to the driving voltage of the analog switch ASW of the sampling circuit block 1a. In the example of FIG. 22, a voltage-driven level shifter LS-6Tr made up of 6 transistors is used as the level shifter, and the output signal of the LS-6Tr is used as a sampling pulse SMP. The sampling pulse SMP (i) is produced from the output pulse of the output signal Q (i).
Accordingly, the rise of the sampling pulse of FIG. 25 is delayed from the rise of the output pulse by a delay time Td-rise, that is equal to the delay time of the delay circuit delay+the delay time Td-rise of the level shifter LS-6Tr. Further, the fall of the sampling pulse is delayed from the output pulse by the delay time Td-fall in the level shifter LS-6Tr.
Further, Document 2 (Japanese Laid-Open Patent Applications Tokukaihei 05-216441 (published on Aug. 27, 1993)), Document 3 (Tokukaihei 05-241536 (published on Sep. 21, 1993)), and Document 4 (Tokukaihei 09-212133 published on Aug. 15, 1997) also describe methods of delaying the rise of a sampling pulse to be later than the fall of the immediately preceding sampling pulse.
As described, the conventional method causes some delay of the rise of the sampling pulse to avoid the overlap of the sampling pulses that interferes charging of the source bus lines or the pixels. However, with the development of high-resolution display, a larger number of gate bus lines or source bus lines are required for the same 1-frame driving, and therefore the charging of one source bus line has to be performed in a shorter time. Therefore, the shift register used in the gate driver or the source driver needs to be driven at high frequency.
As shown in FIG. 25, the fall of the sampling pulse have to occur within the data input valid period of the video signal DATA. Therefore, for example, if the sampling is set to complete at the mid-point of the video signal supplying period when there is no delay of the fall of the sampling pulse, it is necessary that the range of delay should fall within the later half of the video signal supplying period to properly carry out the sampling. This allowable range of the delay time is decreased as the frequency increases, but the same degree of internal delay occurs in the signals of the source driver even at a high-frequency drive. Therefore, even when the rise of the sampling pulse is delayed, there still is a possibility that the fall of the sampling pulse overlaps with the video signal supplying period of the next stage, unless the switching timing of the video signal in high frequency driving is changed. Particularly, the delay time Td-fall of the level shifter LS-6Tr, that is commonly used to convert the power-source voltage level, is relatively large. Therefore, the entire delay of the fall of the sampling pulse becomes more significant, thus more easily inducing the overlap the video signal supplying period in adjacent stages.
When the sampling time of the video signal DATA is shorter than the data input valid period, the sampling is properly carried out. On the other hand, when the sampling time of the video signal DATA is longer than the data input valid period, some writing defects, such as shifting in phase, or incomplete charging may occur. Accordingly, as shown in FIG. 25, the sampling margin, denoted by a difference between the fall of the sampling pulse and the ending timing of the data input valid period, needs to be given. Also, it is important to provide an interval between the sampling pulses that is denoted by the difference between the fall of the corresponding sampling pulse and the rise of the next-stage sampling pulse. When the rise of the sampling pulse of the next stage occurs before the fall of the sampling timing of the current stage, the sampling of the current stage may fail.
Besides, the load tends to increase as the number of pixels increase. Therefore, the charging condition of the source bus line becomes more severe, and there will be serious difficulties in reducing the charging time of the source bus line. Namely, in the foregoing example, assuming that some of the delay times are small because of the variation of delay time, there will be a difficulty in causing the fall of the sampling pulse before the mid-point of the video supplying period.
Therefore, reduction of the variation in the delay of the fall of the sampling pulse is required, meaning that the delay of the fall of the sampling pulse needs to be reduced.
Under such circumstances, reduction of the internal delay time and securement of the charging time are indispensable in a circuit design that deals with high-frequency driving.